Current state of the art semiconductor integrated circuit manufacturing process usually includes various steps that are organized or grouped into different process modules. One such process module, for example, may include a series of steps that creates a pattern of one or more semiconductor devices on a silicon wafer. In particular, this process module may include a lithographic step during which imprints (usually a collection of polygons) on a photo-mask may be projected, through photo-exposure, onto a photo-sensitive resist (“photo-resist”) material that is applied or coated on top of a silicon wafer to create a pattern. Next, the pattern created in the photo-resist material may be transferred or copied down to the underneath silicon wafer through, for example, an etching process as part of another process module that forms semiconductor devices in the wafer.
In general, optical systems currently used in performing photo-exposure or lithographic exposure have certain limitations on achievable feature resolutions. For example, there is always a limit on the size and the number of polygons, measured by density in unit area, that may be satisfactorily transferred from a photo-mask to a silicon wafer with acceptable quality by an optical system. In recent years, despite steady improvement in optical systems, resolutions of these optical systems have not been able to keep up with the increasing demand of manufacturing semiconductor devices of ever smaller feature sizes on a single silicon wafer. Under this circumstance, as an alternative measure to meet the demand for optical system resolution, the concept of Optical Proximity Correction (OPC) was introduced.
In an ideal world, forms of device shapes manufactured on a photo-mask shall truly reflect those to be created or imprinted on a semiconductor wafer. Nevertheless, the concept of an OPC technique is to manipulate or pre-distort forms of device shapes to be manufactured on the photo-mask, as is well known in the art, such that the pre-distorted shapes imprinted on the photo-mask, when being transferred to a semiconductor wafer through photo-exposure and subsequent etching step will eventually produce desired device shapes on the semiconductor wafer. OPC is a software algorithm that takes a set of input design data for a particular lithography step, transforms that input design data by applying a set of pre-determined algorithms and/or models, and finally outputs a new set of design data. This new set of design data is then used in writing or creating patterns in a physical medium such as a photo-mask.
At the center of the OPC technique is various models. The job of these models is to provide reasonably accurate prediction in the simulation world what will happen in the real world. Using these models, an OPC engine (or simulation software) will then provide corrections for errors found in the computational world and apply these corrections to the real world errors. In order to create a model that is suitable for OPC application, the first step is normally to put or lay features of known dimensions on a test mask. This test mask is then used to print and create a corresponding test wafer. During this process, each feature on the test mask needs to be measured because the mask manufacturing process is not always perfect and the features printed on the mask may deviate from what were intended to be printed. In the meantime, each feature on the test wafer needs to be measured as well. However, the measuring of these features usually takes a significant amount of time and has been known as a bottleneck of the OPC process. Based upon the measurement results from both the test mask and the test wafer, a model may be created that can then be used to predict the real world wafer shape for a given mask shape.
In reality, in order to provide relatively accurate prediction of the real world wafer shape, enough sample structures shall be test printed and measurement for each sample structure be made such that they represent as much, and as close, as possible to a full catalogue of geometries that may be included in any actual circuit designs. However, since the range of test structures is generally very large, not only is a large range of dimensions needed for each type of structures, but many different shapes of geometries are also needed to be test printed and their associated features be measured. It is always desirable to shorten the process of model calibration.